1. Field of the Invention
This disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including storage nodes and resistors and a method of manufacturing the same.
2. Description of the Related Art
Along with the development of techniques to manufacture semiconductor devices, transistors have become smaller in size and the integration of semiconductor devices has advanced at a rapid pace. In particular, the integration of Dynamic Random Access Memory device (DRAM) has improved rapidly with the development of processing techniques and recently 1 Giga-bit DRAM was developed.
Conventionally, DRAM has a one-transistor/one-capacitor (1T1C) structure. Cell capacitors may be classified as stack-type capacitors or trench-type capacitors. Stack-type DRAM uses various methods to ensure a sufficient cell capacitance in a narrower area. One of these methods is to form a cylinder shaped storage node (One Cylinder Storage: OCS). Since an OCS-type capacitor has a wide available surface area including all the inner and the outer surfaces of its cylindrical structure, the OSC-type capacitor is highly regarded because it can be subjected to substantial mass-production in correspondence with design rule reduction.
However, the OCS-type capacitor has a high probability of causing a failure such as a two-bit failure, in which the storage nodes lean to one side or collapse as a result of the design rule reduction. This is because the intervals between storage nodes and the widths of storage electrodes have been greatly reduced.
FIG. 1 is a plan diagram illustrating a conventional semiconductor memory device including storage nodes.
Referring to FIG. 1, storage nodes 50 of a conventional OCS-type capacitor are arranged along bit lines 30 and gate lines 20 that are orthogonal to each other. The arrangement of the storage nodes 50 forms isolation areas on a semiconductor substrate.
When DRAM has a design rule of 0.1 μm, the longitudinal length of a storage node 50 is about 300 nm and the width thereof is about 120 nm. The interval between such storage nodes is only about 80 nm. Also, to ensure a sufficient capacitance, the height of the storage node 50 should be greater than 15000 Å.
Thus, the height-to-width ratio of the storage node 50 is generally greater than 12. That is, the height of the storage node is considerably higher compared to its width. Also, the interval between the storage nodes 50 is considerably narrow compared to the height of the storage nodes. Accordingly, a probability that the storage nodes 50 lean to one side or collapse is very high. Also, if the storage nodes 50 lean to one side or slightly lean to one side, the storage nodes may contact one another. If the storage nodes 50 contact one another, a two-bit failure (described above) will occur. Furthermore, the probability of a two-bit failure greatly increase if the design rule is reduced below 0.1 μm.
The phenomenon that the storage nodes 50 leans to one side is related to the arrangement of the storage node 50 as described above with reference to FIG. 1.
Accordingly, efforts are being made to change the arrangement of the storage nodes, for example, to increase the intervals between the storage nodes and to form the storage nodes in a square shape or a rhombus shape, etc.
However, as shown in FIG. 1, the storage node 50 overlaps a storage node contact plug 41 formed on an active area 11 of the semiconductor substrate. If the location of the storage node 50 is changed, the storage node 50 may not overlap the storage node contact plug 41. Also, since the storage node contact plug 41 should be electrically isolated from bit line contact plugs 45 which electrically connect the bit lines 30 with the active areas 11 of the semiconductor substrate, it is very difficult to change the location of the storage node contact plug 41.
A promising method for manufacturing DRAM with a sufficient cell capacitance is to use high-dielectric materials. That is, research is actively carried out on methods that form a dielectric film for a capacitor using materials with a great dielectric constant such as a tantalum oxide film or BST (BaSrTiO3) film.
However, when a dielectric film is formed with high-dielectric materials, it is difficult to form storage nodes and/or upper electrodes of a capacitor with polysilicon as in a conventional technique. This is because high-dielectric material such as a tantalum oxide film or BST is reactive with polysilicon. Such reaction of a dielectric film and polysilicon may deteriorate the electrical properties of the cell capacitor. Accordingly, research has been carried out on methods to form the storage nodes and/or the capacitor upper electrodes with different materials in order to avoid the above-described problem while maintaining the advantages of the high-dielectric materials. Particularly, research has been actively carried out on Metal-Insulator-Semiconductor (MIS) capacitors and Metal-Insulator-Metal (MIM) capacitors.
Also, resistors are formed on a core/perimeter area (not shown) in order to obtain a desired voltage different from an input voltage. In a case where a capacitor is made with polysilicon, these resistors can be formed together when capacitors are formed on a memory cell array area. However, if the capacitor electrodes are formed with metal materials, the resistors cannot be formed together when the capacitors are formed. This is because resistors formed with metal materials have a resistance lower than polysilicon and accordingly a desired voltage cannot be obtained. Therefore, when capacitors are formed with metal materials, an additional process that forms resistors using polysilicon on a core/perimeter area is necessary.
Embodiments of the invention address these and other disadvantages of the conventional art.